1. Technical Field
The present invention relates generally to a bipolar transistor, and more particularly, to a bipolar transistor having a raised extrinsic base with selectable self-alignment and methods of forming the transistor.
2. Related Art
Bipolar transistors with Silicon-Germanium (SiGe) intrinsic base are the focus of integrated circuits fabricated for high performance mixed signal applications. The emitter to collector transit time of such a transistor is reduced by optimizing the Ge/Si ratio, doping profile, and film thickness of the epitaxy grown intrinsic SiGe base. The first developed bipolar transistors to take advantage of the SiGe intrinsic base had an extrinsic base formed by implantation of the silicon substrate. The performance of such transistors reached a limit as the emitter dimension is reduced due to loss of intrinsic base definition caused by the lateral diffusion of the extrinsic base dopants. To achieve higher electrical performance, the transistors must have a doped polysilicon extrinsic base layer on top of the epitaxy grown intrinsic SiGe base, i.e., a raised extrinsic base. Transistors with a raised extrinsic base on top of a SiGe intrinsic base have demonstrated the highest cutoff frequency (Ft) and maximum oscillation frequency (Fmax) to date. See B. Jagannathan et. al., “Self-aligned SiGe NPN transistors with 285 GHz fMAX and 207 GHz fT in a manufacturable technology,” IEEE Electron Device Letters 23, 258 (2002) and J. S. Rieh et. al., “SiGe HBTs with cut-off frequency of 350 GHz,” International Electron Device Meeting Technical Digest, 771 (2002).
FIG. 1A shows a prior art non-self aligned bipolar transistor 10 with polysilicon raised extrinsic base 12 formed by a simple method. In this case, an emitter 14 opening is formed with RIE etch through the oxide/polysilicon stack and stops on a dielectric layer (e.g. oxide) landing pad 18. Landing pad 18 is formed and defined with a lithography step prior to the deposition of the oxide/polysilicon stack. Fmax of such a non-self aligned transistor is limited by a base resistance (Rb) caused by the large spacing between the emitter 14 and extrinsic base 12 in intrinsic base 20. As can be seen in FIG. 1A, this spacing is determined by a remaining portion of the dielectric etch stop layer (or landing pad 18), which may be non-symmetric around emitter 14 due to lithography alignment tolerance.
To minimize base resistance Rb and achieve a high Fmax, the emitter and the extrinsic base polysilicon must be in close proximity. Such structure is shown in FIG. 1B as a prior art self-aligned bipolar transistor 22 with polysilicon raised extrinsic base 24 and a SiGe intrinsic base 26. Transistor 22 is self-aligned, i.e., the spacing between extrinsic base 24 polysilicon and an emitter 30 polysilicon is determined by a sidewall spacer 28 rather than by lithography. A few different methods of forming a self-aligned bipolar transistor with raised polysilicon extrinsic base have been documented. U.S. Pat. Nos. 5,128,271 and 6,346,453 describe approaches in which the extrinsic base polysilicon over a pre-defined sacrificial emitter is planarized by chemical mechanical polishing (CMP). In these approaches, a dishing effect of the CMP process can lead to a significant difference in the extrinsic base layer thickness between small and large devices, as well as between isolated and nested devices. In other approaches described in U.S. Pat. Nos. 5,494,836, 5,506,427, and 5,962,880, an intrinsic base is grown using selective epitaxy inside an emitter opening and an undercut formed under the extrinsic base polysilicon. In these approaches, the self-alignment of the extrinsic base is achieved with the epitaxial growth inside the undercut. Special techniques are required to ensure a good link-up contact between the intrinsic base and the extrinsic base. Each of the approaches described above has significant process and manufacturing complexity.
In view of the foregoing, there is a need in the art for an improved bipolar transistor with a SiGe intrinsic base and with a raised extrinsic base in close proximity to the emitter, and a method of fabricating such a transistor that does not suffer from the problems of the related art.